1. Field of the Invention
The present invention relates to memory devices based on multi-level cells (“MLCs”), and more particularly to techniques for programming charge-trapping sites in two-sided charge-trapping cells.
2. Description of Related Art
Conventional flash memory cells store charge on a floating gate (typically doped polysilicon). The stored charge changes the threshold voltage (Vth) of the memory cell. In a READ operation, a read voltage is applied to the gate of the memory cell, and whether or not the memory cell turns on (e.g. conducts current) indicates the programming state of the memory cell. For example, memory cell that conducts current during a READ operation might be assigned a digital value of “1”, and a memory cell that does not conduct current during a READ operation might be assigned a digital value of “0”. Charge is added to and removed from the floating gate to program and erase the memory cell, i.e., to change the stored value from 1 to 0.
Another type of memory uses a charge-trapping structure, such as a layer of non-conductive SiN material, rather than the conductive gate material used in floating gate devices. When a charge-trapping cell is programmed, the charge is trapped and does not move through the non-conductive layer. The charge is retained by the charge trapping layer until the cell is erased, retaining the data state without continuously applied electrical power. Charge-trapping cells can be operated as two-sided cells. That is, because the charge does not move through the non-conductive charge trapping layer, charge can be localized on different charge-trapping sites.
FIG. 1A is a Cross Section of a Two-Sided Charge-Trapping Cell 100. The two-sided charge trapping cell stores two values, here represented by a left charge-trapping site 108 and a right charge-trapping site 110. The terms “left” and “right” are used merely for purposes of convenient discussion and illustration. Each charge-trapping site of the cell 100 can be programmed to any one of multiple levels. For example, the left charge-trapping site can be programmed to one of four levels L0, L1, L2, or L3, and the right charge-trapping site can be programmed to one of four levels L0, L1, L2, L3 (see FIG. 1B). The programming value of each charge-trapping site represents a data value, such as 11, 01, 00, and 10; however, these data values are merely exemplary and other data values are alternatively assigned to the programming levels.
The two-sided charge-trapping cell 100 has a gate electrode 102, a first dielectric isolation layer 104, a charge-trapping layer 106 having the first (left) charge-trapping site 108 and the second (right) charge-trapping site 110, and a second dielectric isolation layer 112. Charge-trapping cells are well-known in the art of non-volatile memory devices and a detailed description of the cell structure and materials is therefore omitted.
The two-sided charge-trapping cell 100 is fabricated on a substrate 114, such as a silicon wafer or other semiconductor, and has source/drain regions 116, 118. The cell is programmed by biasing the terminals of the device so as to transfer or remove charge from the charge-trapping sites 108, 110. A data value stored by a charge-trapping site of the cell is read by applying a read voltage to the gate electrode 102 and sensing the current flowing between the source/drain regions 116, 118. Whether a source/drain region is operating as a source or as a drain depends on the bias conditions, so these physical structures will be referred to as “source/drain regions” for purposes of convenient discussion.
The two-sided charge-trapping cell can be programmed to different levels in the first and second charge-trapping sites 108, 110. In other words, the left charge-trapping site 108 is programmed to a different level (data value) than the right charge-trapping site 110. Two-sided charge-trapping cell programming and reading techniques are well-known in the art of charge-trapping memory cell devices and a detailed discussion is therefore omitted.
FIG. 1B shows a memory cell distribution versus READ voltage (Vt) for an MLC memory array having charge-trapping cells. The charge-trapping cell has four levels, L0, which is the erased condition, and programming levels L1, L2, and L3, which are levels where increasing amounts of charge have been transferred to the charge-trapping sites of the charge-trapping cell, increasing Vt for each successive programming level. A site in a charge-trapping cell is typically programmed by programming the cell to a preliminary program-verify value (PV1′, PV2′, PV3′) using a first programming technique, and then programming the cell to a final program-verify value (PV1, PV2, PV3) using a second programming technique. The second programming technique typically provides more precise control of the Vt levels, which results in a more narrow Vt distribution and wider read windows (e.g. RW12, RW23) between programmed levels. Wide read windows are desirable to facilitate READ operations. The data values 11, 01, 00, 10 are arbitrarily assigned to the programming levels L0, L1, L2, L3 for purposes of illustration and discussion. In a two-sided charge-trapping cell, each charge-trapping site can be operated as a multi-level site. That is, the left charge-trapping site can be programmed to multiple levels independently from the right charge-trapping site, which can also be programmed to multiple levels.
While the right and left charge-trapping sites of a charge-trapping cell (see FIG. 1A, ref. nums. 108, 110) can be independently programmed and read, an interaction arises between the charge-trapping sites that is commonly known as the “neighbor effect.” The neighbor effect is basically that the programmed value of one charge-trapping site, and the programming biases applied to achieve that programmed value, can affect the other charge-trapping site, causing a shift in the threshold voltage Vt in the neighboring site. It is desirable to program two-sided charge-rapping memory devices in a manner that reduces the neighbor effect.